1. Field of the Invention
The present invention relates to a semiconductor device such as an LSI device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device with multiple levels of metal interconnects in which copper trench interconnects are used and a manufacturing method thereof.
2. Description of the Related Art
In recent years, the increase in high-speed operation and increased integration in the LSI device have proceeded, and there have arisen demands that further miniaturization and more densely spaced arrangement should be attained not only in the transistor but also in the interconnect.
As a metal interconnect material, mainly Al is utilized, hitherto, but this is known to lead to a problem of electromigration (EM); that is, a temperature rise due to an increase in current density of the interconnect and a heat generated by the whole device causes some metal atoms within an interconnect layer to move, which creates voids in some parts from which those atoms move out and may thereby bring about the severance of the interconnect. Further, in some parts where metal atoms are accumulated, grains called hillocks are formed and, cause stress on a dielectric layer lying over the interconnect, these may cause cracks.
To solve such problems, the use of an alloy in which a very small amount of Si or Cu is mixed with Al is proposed, but even this will become insufficient if attempts to attain further miniaturization and more densely spaced arrangement advance, and, therefore, the use of the copper interconnect which has a still higher reliability is under consideration.
Among metal materials, copper has the second lowest resistivity to silver (1.7 to 1.8 .mu..OMEGA.-cm, as against 3.1 .mu..OMEGA.-cm for AlCu) as well as an excellent EM reliability. Consequently, amidst the advance in achieving a still more densely spaced arrangement, establishment of novel techniques making use of these copper characteristics is very much sought after.
For instance, techniques wherein copper is employed as an interconnect material are disclosed in an article titled "A High Performance 1.8 V, 0.20 .mu.m CMOS Technology with Copper Metallization" in IEDM (International Electron Devices Meeting) '97, pp. 769-772, and an article titled "Full Copper Wiring in a Sub-0.25 .mu.m CMOS ULSI Technology" in IEDM '97, pp. 773-776.
Copper is a relatively difficult material to have a pattern formed therefor by etching. Especially, in the application to a semiconductor device of sub-0.25 .mu.m order, copper should be formed by the interconnect trench-burying techniques (the damascene metallization techniques).
This is carried out, for example, as shown from FIG. 5(a) to FIG. 5(e). Firstly, a first interconnect trench (2) is formed on a first interlayer dielectric film (1) (FIG. 5(a)), and then a barrier metal layer (3) and copper (4) are grown thereon, in succession, by the electroplating method, the CVD (Chemical vapour Deposition) method or the like (FIG. 5(b)). Subsequently, polishing by the chemical mechanical polishing (CMP) method is applied thereto till the surface of the first interlayer dielectric film (1) is exposed, and, with planarization of the copper surface, a first-level interconnect (5) is accomplished in the form of damascene (FIG. 5(c)). In order to form a copper interconnect above this, after a second interlayer dielectric film (7) is grown, a second interconnect trench (9) as well as a via hole (8) for a contact with the first-level interconnect (5) are formed by means of photolithography (FIG. 5(d)) and then, by filling with copper in the similar manner, a second-level interconnect (10) is formed (FIG. 5(e)).
When the second interconnect trench (9) as well as the via hole (8) are formed in the second interlayer dielectric film (7), reflection from the underlying first-level interconnect (5) during the resist exposure may cause an overexposure and result in a collapse of the resist pattern, which is a serious problem. Especially, in the case that a widely spaced pattern and a closely spaced pattern are mingled due to the device miniaturization, if the exposure is conducted under conditions adjusted to the widely spaced part, the closely spaced part is exposed excessively and this overexposure makes the pattern collapse significantly. On the other hand, if the adjustment of the exposure is made to the closely spaced part, the widely spaced part is underexposed so that the pattern therein is not sufficiently defined. Certainly, it is preferable that every part can be exposed uniformly, and, consequently, formation of an anti-reflective coating (ARC) becomes essential.
As the ARC, the organic ARC of polyimide or the like and the inorganic ARC of Si, SiN, TiN, TiW or the like are known hitherto. In addition, the use of the ARC of SiON has been proposed. In the case of the organic ARC, however, its effect appears only when formed to a thickness of several hundred nm or so and, moreover, with a coating method such as the spin coating method being utilized, it is difficult to form as a flat film. Consequently, the application thereof to a minute device in which copper interconnects are employed is not very feasible. With the ARC such as SiON grown under the condition of the atmosphere containing oxygen, copper may be oxidized. The formed copper oxide film is easily peeled off and, in some cases, a desired ARC cannot be formed. Further, for the nitride ARC, there are problems described below, with reference to FIG. 6. That is, a portion of the nitride film in contact with a lower-level copper interconnect (61) must be removed in a later step of the manufacturing process, and, in that occasion, while etching is applied to both an oxide film (63) and the nitride film (62), etching conditions, being set respectively, must be changed in the middle of the etching step. Furthermore, particularly because the film thickness of the nitride film (62) is uneven in forming, overetching is normally required. This makes a lateral section of the nitride film (62) recede, as shown in FIG. 6(a).
Meanwhile, if copper comes into a direct contact with an oxide film, the surface of copper is oxidized when heated in a later step. Further, there is another problem that, if copper diffuses into a substrate through the oxide film, the device properties are led to deteriorate. Accordingly, in a normal practice, a barrier film (TiN, WN or the like) is set between the dielectric film and copper. If the formation of the barrier film is carried out in such a state that the lateral section of the nitride film is receded as described above, however, the barrier film formed by the sputtering method or the like cannot reach the lateral section and the barrier film (64) can be formed only in the shape, for example, as shown in FIG. 6(b). Consequently, if metallization with copper by the ordinary CVD method is performed thereon, copper goes round and comes into a direct contact with the dielectric film, which may give rise to problems described above.
On the other hand, in Japanese Patent Application Laid-open No. 112201/1994, there is disclosed novel techniques in which the upper part of a tungsten interconnect is subjected to oxidation and a tungsten oxide film is formed and said tungsten oxide film serves as an anti-reflective layer. In this case, etching can be carried out in a later step of the etching process, using fluorine gas alone, which is an advantage.
The oxide film of copper, however, has a problem that, generally, it is not very dense and easily peeled off and, hitherto, it was a widely accepted view that copper should be formed so as not to be oxidized.